The present invention relates to testing interconnected assemblages of integrated circuits and, more particularly, to testing interconnected assemblages of integrated circuits having portions of the testing system incorporated into those integrated circuits.
The costs of providing various kinds of circuit capabilities in an integrated circuit has been decreasing rapidly. This decrease is due to a number of factors, but primarily it is because of the increase in the density of circuits which can be provided in an integrated circuit.
This decrease in costs of integrated circuits is, of course, leading to a very rapid increase in the numbers of such integrated circuits being used. One manner in which this increased use comes about is that designers of systems are taking advantage of these reduced costs to increase the capabilities of the systems they are improving with new designs, and this often means that larger numbers of such integrated circuits are being used in many kinds of upgraded systems. Of course, many entirely new kinds of systems can also be designed with these circuits in view of the reduced cost in using them.
This evolving integrated circuit situation has lead to substantial difficulties in testing such integrated circuits, and in testing such assemblages of integrated circuits, because such large densities of circuits in an integrated circuit means that larger numbers of circuit nodes are not externally available at which to conduct tests. Similarly, such large numbers of circuits in an integrated circuit lead to a larger number of input and output connections to each such integrated circuit. Thus, in assemblages of such integrated circuits, there will be a resulting large increase in the number of interconnections between the various integrated circuits mounted on a circuit board or other similar structure, and between the integrated circuits and the input and output connections on such boards or structures, all of which are usually desired to be tested.
As a result, provisions are being made for incorporating test circuits into the integrated circuits themselves and, often, additional separate test circuits are provided either on the structures upon which these integrated circuits are mounted or on a separate test structure that is interconnected to the other integrated circuit mounting structures, or both. Some test circuits incorporated into the integrated circuits are primarily concerned with setting the states of internal latches in the operating circuitry or monitoring, i.e. scanning, output states of such latches and other circuit nodes therein, such as occurs using the level sensitive scan design (LSSD) methodology. Alternatively, other test circuits are primarily involved with the setting of conditions at inputs of the operating circuits in integrated circuits and monitoring conditions at the outputs of such operating circuits in the integrated circuits, as in the boundary scan methodology.
Whatever the test circuits incorporated in an integrated circuit for testing purposes in implementing the corresponding test methodology, one difficulty which arises during testing is the occurrence of circuit faults which do not exhibit the same result during testing from one test to another. Such faults can be due to a faulty interconnection which intermittently opens and closes, or to an open interconnection having one end connected to a relatively high impedance. In this latter situation, various leakages can result in the interconnection portion connected to the relatively high impedance having a voltage change occur thereon which may more or less randomly reach one of the specified logic state voltage levels or any other value therebetween. Situations such as these lead to unreliable fault detection.
Because the circuitry provided in integrated circuits has become quite reliable, a large fraction of such failures occurs in the interconnections between chips or between chips and the edge connection of the circuit board or other structure upon which such chips are mounted, or the interconnections between such boards or structures. These interconnections include the portions thereof on the surface of the integrated circuit mounting structure all the way through the input and output terminal pads, or input and output terminal regions, in the integrated circuits. Thus, there is a desire to provide a known signal value on the input of an integrated circuit mounted on such a structure to assure test repeatability, even though the interconnection to that input may be an open circuit or an intermittently open circuit.